1. Field of the Invention
The present invention relates to a semiconductor device having a MOS transistor formed on an SOI substrate.
2. Description of the Background Art
FIG. 20 is a perspective view showing a cross section of a conventional semiconductor device M90 having a field isolation structure which is the background of the present invention. The semiconductor device M90 is an SOI semiconductor device in which an SOI substrate including a semiconductor layer in film form, or an SOI (semiconductor-on-insulator) layer, which is formed on an insulating substrate is used as a semiconductor substrate into which transistor elements and the like are manufactured.
As shown in FIG. 20, the semiconductor device M90 comprises a silicon semiconductor layer as the SOI layer 3 formed on the insulating substrate including a supporting substrate 1 and a buried oxide film 2. The SOI layer 3 includes a great number of element regions wherein NMOS transistors are to be formed and a great number of element regions wherein PMOS transistors are to be formed. Planar field-shield electrodes (abbreviated hereinafter as “FS electrodes”) 5 for electrical isolation of these element regions are formed on the boundaries of the element regions in the SOI layer 3.
The FS electrodes 5 shown in FIG. 20 are arranged in parallel and predetermined spaced relation on the SOI layer 3 so as to define active regions in the respective element regions. The FS electrodes 5 are covered with field-shield insulating layers 4 (abbreviated hereinafter as “FS insulating layers”). Gate electrodes 6 are disposed each of which extends from the top of an active region to the tops of two parallel FS insulating layers 4. Gate oxide films 10 are formed between the gate electrodes 6 and the active regions. The FS insulating layers 4 are made of an oxide to provide electrical insulation between the FS electrodes 5 and the gate electrodes 6.
Source and drain regions (not shown in FIG. 20) in the SOI layer 3 are electrically connected to drain and source electrodes (not shown in FIG. 20) through contact holes 7 provided in an insulating layer not shown. The gate electrodes 6 are connected to gate interconnect lines (not shown in FIG. 20) through contact holes 8.
A body contact electrode (not shown in FIG. 20) is connected through a contact hole 9 to the SOI layer 3. Although the contact hole 9 connected to the body contact electrode is shown in FIG. 20 as passing through the FS electrode 5 and connected to the SOI layer 3, it is also common to provide the contact hole 9 on the SOI layer 3 outside the FS electrode 5.
In the semiconductor device M90, the SOI layer 3 in an isolation region is cut off by applying 0 V in an NMOS structure or a power supply voltage Vcc in a PMOS structure to the FS electrodes 5. This results in electrical isolation between the element regions.
The SOI layer 3 may include a body portion which is floating rather than the body potential fixing contact hole 9 in the structure of FIG. 20.
FIG. 21 is a cross-sectional view of an NMOS transistor having an SOI structure in which a body portion is floating.
Referring to FIG. 21, the buried oxide film 2 is formed on the supporting substrate 1, and the SOI layer 3 is formed on the buried oxide film 2. An N-type drain region 11 and an N-type source region 12 are selectively formed in the SOI layer 3. A P-type region of the SOI layer 3 which includes a body region between the drain and source regions 11 and 12 is defined as a body portion 13.
The gate oxide film 10 is formed on the body portion 13 between the drain and source regions 11 and 12, and the gate electrode 6 is formed on the gate oxide film 10.
In the SOI MOS transistor constructed as above described, if the potential of the body portion 13 is not fixed, a body potential BV is changed by the influences of signals flowing through the drain region 11 and the source region 12 and the like, accordingly changing the operating speed VC of the MOS transistor, as shown in FIG. 22. It should be noted that the relationship of FIG. 22 between the body potential and the operating speed is shown as relative values on the basis of time=0.
One of the solutions to the above described drawback is to fix the potential of the body portion 13 by providing the body potential fixing contact hole 9 shown in FIG. 20 and the like. FIG. 23 schematically illustrates a MOS transistor structure wherein the body potential is fixed. As shown in FIG. 23, the potential of the body portion 13 is fixed by a body terminal PB1.
An alternative solution is to provide a DT (Dynamic Threshold) MOS structure as shown in FIG. 24 in which the gate electrode 6 and the body portion 13 are short-circuited and a body terminal PB2 applies a common potential to the gate electrode 6 and the body portion 13.
Conventional SOI MOS transistors are capable of stabilizing the operating speed which is relatively low by fixing the potential of the body portion 13 as depicted in FIGS. 23 and 24.
However, a high-speed operation in synchronism with a clock having an operating frequency of not less than 500 MHz imposes very stringent requirements for the timing of signal passing between circuits. This causes even the MOS transistors having the structures of FIGS. 23 and 24 to encounter a phenomenon similar to that caused in the case where the body portion 13 is floating. This phenomenon affects the operating speed of such MOS transistors, for example, an unstable operation thereof.